Tool Introduction
Basic usage of the verification tool.
Environment Usage
Detailed usage instructions for the Open Verification Platform environment.
Categories:
This page will briefly introduce what verification is and concepts used in the examples, such as DUT (Design Under Test) and RM (Reference Model).
Waveform Generation
Generate circuit waveforms.
Multi-File Input
Handling multiple Verilog source files
Coverage Statistics
Coverage tools
Integrated Testing Framework
Available Software Testing Frameworks
Internal Signals
Internal Signal Example