Environment Usage

Detailed usage instructions for the Open Verification Platform environment.

This page will briefly introduce what verification is and concepts used in the examples, such as DUT (Design Under Test) and RM (Reference Model).


Tool Introduction

Basic usage of the verification tool.

Waveform Generation

Generate circuit waveforms.

Multi-File Input

Handling multiple Verilog source files

Coverage Statistics

Coverage tools

Integrated Testing Framework

Available Software Testing Frameworks

Internal Signals

Internal Signal Example

Last modified May 7, 2025: fix(multilang): sync en with cn (963533f)