In this verification task, you will get close to the StoreUnit module of the XiangShan Kunming Lake architecture, understand the design philosophy of XiangShan’s memory address execution unit, and deepen your understanding of the RISC-V instruction set architecture. Welcome to participate! (Sign-up link here, QQ group: 600480230).

StoreUnit is used for address generation and processing of Store-type instructions. It is a key component of the Load/Store pipeline and, together with LoadUnit, forms the LSU (Load Store Unit) memory access pipeline. In terms of functionality, LSU is responsible for the specific execution flow of memory-access instructions, including normal memory address space and peripheral-related MMIO address space, as well as atomic instruction execution. In terms of flow, LSU receives instructions issued from the reservation station. According to the type of memory access instruction, it goes through different instruction pipelines, obtains instruction execution results, writes back to ROB, notifies the forward bypass network, wakes up subsequent related instructions, and forwards data.

Task Introduction

This verification task is to verify the functional points of the StoreUnit module, with a total of 18 micro-tasks released. Participants can choose the tasks they are interested in and complete one or more.

Micro-tasks are functional breakdowns of the module under verification. Each functional point corresponds to a packaged function. As a participant, you only need to complete the corresponding function to proceed with verification. Each micro-task provides a function template. You only need to select the provided corresponding function, write test cases to verify the corresponding functionality, and complete the verification report. Excluding preliminary learning time, each micro-task takes approximately 2-5 hours to verify. Each micro-task has a cash reward. We will issue cash rewards to the first five people who successfully complete the task. In addition, if you find a bug for the first time during the verification process and contact us to confirm it, you will receive an additional bonus ๐Ÿ’ด

The task participation process is as follows:

Task Process
Task Process
All tasks will be assigned through XS-MLVP XiangShan Processor Issues.

The recommended completion time is comprehensively calculated based on factors such as difficulty of understanding and workload. Generally, tasks requiring 1-2h are easy, tasks requiring 3-4h are of moderate difficulty, possibly with large workload or requiring certain time to understand hidden task information, and tasks taking 5h or more are difficult, generally with both large workload and high difficulty of understanding. The recommended time does not include time needed for learning and environment installation and configuration.

LSU-StoreUnit Detailed Verification Document: StoreUnit Verification Document

Task List

All micro-tasks are shown below. You can choose to complete one or more. In each micro-task, the first five students who submit results and pass review will receive the task reward.

Functional PointDifficultyRecommended TimeRewardDetails
1. Scalar Instruction Dispatchโ˜… โ˜… โ˜† โ˜† โ˜†2 hours100 CNYtest_scalar_dispatch function
Memory Instruction Dispatch Function
2. Vector Instruction Dispatchโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_vector_dispatch function
Memory Instruction Dispatch Function
3. Address Pipeline S0 Stageโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_s0_address_calc function
Address Pipeline Function
4. Address Pipeline S1 Stageโ˜… โ˜… โ˜… โ˜… โ˜†4 hours200 CNYtest_s1_raw_check function
Address Pipeline Function
5. Address Pipeline S2 Stageโ˜… โ˜† โ˜† โ˜† โ˜†1.5 hours80 CNYtest_ s2_sq_mark_ready function
Address Pipeline Function
6. Vector Instruction Splitโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_split function
Vector Store Instruction Execution Function
7. Vector Element Offset Address Calculationโ˜… โ˜… โ˜† โ˜† โ˜†2 hours100 CNYtest_offset function
Vector Store Instruction Execution Function
8. TLB Missโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_tlb_miss function
Re-execution Function
9. RAW Violation Detectionโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_violation function
RAW Processing Function
10. RAW Violation Recoveryโ˜… โ˜… โ˜… โ˜… โ˜…5.5 hours270 CNYtest_recovery_mech function
RAW Processing Function
11. SBuffer Mergeโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_write_merge function
SBuffer Optimization Function
12. SBuffer Replacementโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_plru_replace function
SBuffer Optimization Function
13. MMIO Instruction Execution Orderโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_order function
MMIO Processing Function
14. MMIO Exceptionโ˜… โ˜… โ˜… โ˜… โ˜†4 hours200 CNYtest_exception function
MMIO Processing Function
15. NC Out-of-Order Executionโ˜… โ˜… โ˜† โ˜† โ˜†2 hours100 CNYtest_exec function
Uncache Instruction Execution Function
16. Uncache Forwardingโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_forward function
Uncache Instruction Execution Function
17. Scalar Unaligned Instruction Splitโ˜… โ˜… โ˜… โ˜† โ˜†3 hours150 CNYtest_scalar_split function
Unaligned Memory Access Function
18. Unaligned Access Exceptionโ˜… โ˜… โ˜… โ˜… โ˜†4 hours200 CNYtest_exception function
Unaligned Memory Access Function

Deliverable Requirements

  1. Test Cases: Test cases are code deliverables that define input combinations used for testing and expected output combinations.
  2. Verification Report: The verification report is a text deliverable, requiring no less than 500 words, including functionality, input and output results, and boundary condition analysis. Report reference format: Micro-report Template
  3. Other Notes: If your project requires other dependencies to run, you can explain them in the test report or PR.

Participation and Submission

For this verification task, please complete the verification work and submit a PR to the Verification Framework repository provided by UnityChipForXiangShan.

Please fork the above UnityChipForXiangShan repository, complete the verification code and documentation, and then submit a PR when your deliverables are ready.

Reward Information

In the end, according to the difficulty of the tasks and everyone’s completion, you will receive varying amounts of cash rewards. In addition, if you find and report a bug for the LSU StoreUnit module and it is confirmed, you have the opportunity to receive more rewards.

Bug Report

Please directly submit an issue using the bug report template in the UnityChipForXiangShan repository.

When submitting a bug, please first select the “bug need to confirm” label. Then choose the label that best matches your assessment from the four bug severity levels (minor, normal, serious, critical) provided by the labels. Finally, please select the module where you discovered the bug. This verification is for the memory storeunit module, so you can uniformly apply the ut_mem_block.storeunit label.