Module Verification Tasks
Practice UT verification to deepen understanding of the RISC-V instruction set architecture
AI Operator Verification Phase 1: RISC-V Vector Computing Verification Practice (Completed)
UnityChip Hackathon Season 1: Warm-up Challenge (Completed)
UT Practice Session 10: AI Vector Processor — Floating-Point Fused Add Module Verification (Completed)
UT Practice Session 9: Third-Generation XiangShan (Kunming Lake) Architecture LSU-StoreUnit Module UT Verification Practice (Completed)
UT Practice Session 8: Third-Generation XiangShan (Kunming Lake) Architecture L2TLB-bitmap Module UT Verification Practice (Completed)