Verilator Official Website: www.veripool.org/verilator/

Verilator is an open-source simulation and synthesis tool for the hardware description language (HDL) Verilog. It is capable of converting Verilog code into high-performance C++ or SystemC code, enabling simulation and verification of hardware designs. Verilator accelerates the simulation process by executing Verilog code within a C++ environment, thus often achieving faster simulation speeds compared to traditional interpreter-based simulators.

Key features of the Verilator project include:

  1. High-speed simulation: Verilator converts Verilog code into high-performance C++ code, leveraging the computational power of modern computers to provide faster simulation speeds.
  2. Open-source and free: Verilator is an open-source project released under the GNU General Public License (GPL), allowing free usage and modification.
  3. Support for various Verilog features: Verilator supports most features of Verilog-1995, Verilog-2001, and Verilog-2005, as well as some features of SystemVerilog.
  4. Cross-platform: Verilator can run on multiple operating systems, including Linux, macOS, and Windows.
  5. Flexibility: Verilator provides numerous options and parameters for customization according to user requirements, including optimization levels and output formats.
  6. Integration with other tools: Verilator can be integrated with other EDA tools such as simulation and synthesis tools to complete the entire hardware design flow.

In addition to Verilator, other open-source RTL simulators include Icarus, moore, Slang, etc. The level of support for SystemVerilog in open-source simulators can be referenced at: https://chipsalliance.github.io/sv-tests-results/