Progress Overview
This project aims to perform unit testing (Unit Test, UT) verification of the XiangShan Processor Kunming Lake architecture through open-source crowdsourcing. The chart below shows the verification status of each module in the XiangShan Kunming Lake architecture.
Overall statistics are as follows:
| Total Cases: | - | Passed Cases: | - | Passed Rate: | - |
| Failed Cases: | - | Skipped Cases: | - | Skip Rate: | - |
| Function Coverage: | - | Covered Functions: | - | Covered Rate: | - |
| Total Lines: | - | Covered Lines: | - | Covered Rate: | - |
*The total number of lines will continue to increase as DUTs are added, so: the total line coverage is not the final coverage.
Other quick links:
- DUT Documentation & Functions
- Pending Bug List
- Confirmed Bug List
- Fixed Bug List
- Ongoing Task List
- Completed Task List
XiangShan Kunming Lake DUT Verification Progress
Note: The statistics in this document are automatically generated based on test results.
Data auto-update date: 1970-01-01 00:00:00